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HS-6664RH
TM
Data Sheet
August 2000
File Number
3197.4
Radiation Hardened 8K x 8 CMOS PROM
The Intersil HS-6664RH is a radiation hardened 64K CMOS PROM, organized in an 8K word by 8-bit format. The chip is manufactured using a radiation hardened CMOS process, and utilizes synchronous circuit design techniques to achieve high speed performance with very low power dissipation. On-chip address latches are provided, allowing easy interfacing with microprocessors that use a multiplexed address/data bus structure. The output enable control (G) simplifies system interfacing by allowing output data bus control in addition to the chip enable control (E). All bits are manufactured storing a logical "0" and can be selectively programmed for a logical "1" at any bit location. Applications for the HS-6664RH CMOS PROM include low power microprocessor based instrumentation and communications systems, remote data acquisition and processing systems, and processor control storage. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95626. A "hot-link" is provided on our homepage for downloading. www.intersil.com/spacedefense/space.htm
Features
* Electrically Screened to SMD # 5962-95626 * QML Qualified per MIL-PRF-38535 Requirements * 1.2 Micron Radiation Hardened Bulk CMOS * Total Dose . . . . . . . . . . . . . . . . . . . . . . 300 krad(Si) (Max) * Transient Output Upset. . . . . . . . . . . . . .>5 x 108 rad(Si)/s * LET >100 MEV-cm2/mg * Fast Access Time . . . . . . . . . . . . . . . . . . . . . . . 35ns (Typ) * Single 5V Power Supply * Single Pulse 10V Field Programmable * Synchronous Operation * On-Chip Address Latches * Three-State Outputs * NiCr Fuses * Low Standby Current . . . . . . . . . . . . . . <500A (Pre-Rad) * Low Operating Current . . . . . . . . . . . . . . . . . . <15mA/MHz * Military Temperature Range . . . . . . . . . . . -55oC to 125oC
Ordering Information
ORDERING NUMBER 5962F9562601QXC 5962F9562601QYC 5962F9562601VXC 5962F9562601VYC HS1-6664RH/PROTO HS9-6664RH/PROTO INTERNAL MKT. NUMBER HS1-6664RH-8 HS9-6664RH-8 HS1-6664RH-Q HS9-6664RH-Q HS1-6664RH/PROTO HS9-6664RH/PROTO TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000
HS-6664RH Pinouts
28 LEAD CERAMIC (SBDIP) CASE OUTLINE D28.6 MIL-STD-1835, CDIP2-T28 TOP VIEW
NC 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 DQ0 11 DQ1 12 DQ2 13 GND 14 28 VDD 27 P
28 LEAD FLATPACK CASE OUTLINE K28.A MIL-STD-1835, CDFP3-F28 TOP VIEW
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD P
26 NC 25 A8 24 A9 23 A11 22 G 21 A10 20 E 19 DQ7 18 DQ6 17 DQ5 16 DQ4 15 DQ3
NC A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
P must be hardwired at all times to VDD, except during programming.
Functional Diagram
MSB A2 A3 A4 A5 A6 A7 A8 LSB A LATCHED ADDRESS REGISTER 8 A 8 E E 32 32 32 32 32 32 32 32 256 GATED ROW DECODER 256 X 256 MATRIX
1 OF 8
P
8 E E A G E 5
GATED COLUMN DECODER PROGRAMMING, AND DATA OUTPUT CONTROL A 5
8
Q0 - Q7
LATCHED ADDRESS REGISTER
MSB A0 A1 A10 A9 A11 A12
LSB
NOTE:
P must be hardwired at all times to VDD, except during programming.
TRUTH TABLE E 0 0 1 G 0 1 X Enabled Output Disabled Disabled MODE
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HS-6664RH Burn-In Circuits
HS1-6664RH 28 LEAD (8K X 8 PROM DIP) HS9-6664RH 28 LEAD (8K X 8 PROM FLATPACK)
VDD NC A12 A7 A6 A5 A4 A3 A2 A1 A0 NC NC NC DQ0 DQ1 DQ2 VSS VDD P NC A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 NC NC NC NC NC NC F13 F8 F7 F6 F5 F4 F3 F2 F1 LOAD LOAD LOAD NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS VDD P NC A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 LOAD LOAD LOAD LOAD LOAD NC F9 F10 F12 F0 F11 F0
HS1-6664RH 28 LEAD (8K X 8 PROM DIP) HS9-6664RH 28 LEAD (8K X 8 PROM FLATPACK)
VDD
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15 LOAD: 10k OUT
VSS = GND
VSS = GND
VDD/2
STATIC CONFIGURATION NOTES: 1. Power Supply: VDD = 5.5V (Min) 2. Resistors = 10k 10% NOTES: 3. 4. 5. 6. 7. 8.
DYNAMIC CONFIGURATION Power Supply: VDD = 5.5V (Min) VIH = VDD to VDD-1.0V VIL = 0.0V to 0.8V Resistors = 10k 10% F0 = 100KHz 10%, 50% Duty Cycle F1 = F0/2; F2 = F1/2; F3 = F2/2; F4 = F3/2; F5 = F4/2; . . . F13 = F12/2
Irradiation Circuit
HS1-6664RH 28 LEAD (8K X 8 PROM DIP)
VDD NC NC 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 DQ0 11 DQ1 12 DQ2 13 VSS 14 VDD P NC A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 NC
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD = GND
NOTES: 9. Power Supply: VDD = 5.5V 0.5V 10. All Resistors = 47k 10%
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HS-6664RH Die Characteristics
DIE DIMENSIONS: 271mils x 307mils x 19mils 1mils INTERFACE MATERIALS: Glassivation: Type: SiO2 Thickness: 8kA 1kA Top Metallization: M1:6kA 1kA Si/Al/Cu 2kA 500A TiW M2:10kA 2kASi/Al/Cu ASSEMBLY RELATED INFORMATION: Substrate Potential: VDD ADDITIONAL INFORMATION: Worst Case Current Density: 2 x 105 A/cm2 Transistor Count: 110, 874
Metallization Mask Layout
HS-6664RH
(28) VDD (2) A12 (23) A11 (26) NC (25) A8 (24) A9 (7) A3 (6) A4 (5) A5 (4) A6 (3) A7 (27) P (22) G A10 (21)
VSS
GND (14)
DQ0 (11)
DQ1 (12)
DQ2 (13)
DQ3 (15)
DQ4 (16)
DQ5 (17)
DQ6 (18)
DQ7 (19)
A0 (10)
A2 (8)
A1 (9)
E (20)
VDD
VSS VDD
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HS-6664RH
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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